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System Basis Chip
Target Datasheet
1 * * * * * * * * * * * * * * * * * * Features Standard Fault Tolerant differential CAN-Transceiver Bus Failure Management Low current consumption mode <70A CAN Data Transmission Rate up to 125 kBaud Low-Dropout Voltage Regulator 5V 2% Two Low Side Switches Three High Side Switches with internal Charge Pump Power On and Under-Voltage Reset Generator Vcc Supervisor Window Watchdog Flash Program Mode Programable Cyclic Wake Timing via SPI Integrated Fail-Safe Mechanism Standard 16 bit SPI-Interface Wide Input Voltage and Temperature Range Thermal Protection Enhanced Power P-DSO-Package Wakeup Input Pin Ordering Code on request
TLE 6266 G
P-DSO-28-6 Enhanced Power
Type TLE 6266 G
Package P-DSO-28-6
2
Description
The TLE 6266 G is a monolithic integrated circuit in an enhanced power P-DSO-28-6 package, which incorporates a failure tolerant low speed CAN-transceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a 16 bit SPI interface to control and monitor the IC. Further there are integrated additional features like three high side switches, two low side switches, a window watchdog circuit and a reset circuit. The IC offers a low current consumption mode, that reduces the current to typ. 70A. The IC is designed to withstand the severe conditions of automotive applications and is optimized for low-speed data transmission (up to 125 kBaud).
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Pin Configuration (top view)
CANH 1 RTH 2 RO 3 CANL 4 RTL 5 GND 6 GND 7 GND 8 GND 9 OUTH1 10 OUTL1 11 OUTL2 12 OUTH2 13 OUTH3 14
28 WK 27 PWM 26 TxD 25 RxD 24 Vcc 23 GND 22 GND 21 GND 20 GND 19 CLK 18 DI 17 DO 16 CSN 15 Vs
P-DSO-28-6
(enhanced power package)
Figure 1
TLE 6266 Block Diagram
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4 Pin No. 1 2 3 4 5
Pin Definitions and Functions Symbol CANH RTH RO CANL RTL Function CAN-H bus line; HIGH in dominant state CANH-Termination input; connected to CANH via external termination resistor Reset output; open drain output; integrated pull up; active LOW CAN-L bus line; LOW in dominant state CANL-Termination input; connected to CANL via external termination resistor Ground; to reduce thermal resistance place cooling areas on PCB close to this pins. High side output 1; controlled via PWM input and/or SPI input, short circuit protected Low side output 1; SPI controlled, with active zener Low side output 2; SPI controlled, with active zener High side output 2; SPI controlled High side output 3; SPI controlled, in cyclic wake mode controlled by an internal autotiming function Power supply; block to GND directly at the IC with ceramic capacitor SPI interface Chip Select Not; CSN is an active low input; serial communication is enabled by pulling the CSN terminal LOW. CSN input should only be transitioned when CLK is LOW. CSN has an internal active pull up and requires CMOS logic level inputs. See Figure 11 for more details. SPI interface Data Out; DO is a tristate output that transfers diagnosis data to the control device. Serial data transfered from DO is a 16 bit diagnosis word with the Least Significant Bit (LSB) transmitted first. The output will remain 3-stated unless the device is selected by a LOW on Chip-Select-Not (CSN). DO will accept data on the rising edge of CLK-signal; see Table 6 for output data protocol and Figure 11 for more timing details.
6, 7, 8, 9, GND 20, 21, 22, 23 10 11 12 13 14 15 16 OUTH1 OUTL1 OUTL2 OUTH2 OUTH3
VS
CSN
17
DO
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4 Pin No. 18
Pin Definitions and Functions (cont'd) Symbol DI Function SPI interface Data In; DI receives serial data from the control device. Serial data transmitted to DI is a 16 bit control word with the Least Significant Bit (LSB) transferred first. The input has an active pull down and requires CMOS logic level inputs. DI will accept data on the falling edge of CLK-signal; see Table 6 for input data protocol and Figure 11 for more details. SPI interface clock input; clocks the shiftregister; CLK has an internal active pull down and requires CMOS logic level inputs Output voltage regulator; 5V logic supply, block to GND with an 100nF external ceramic capacitor directly at the IC + external capacitor CQ 22 F CAN Receive data output; push-pull output; LOW: bus becomes dominant, HIGH: bus becomes recessive CAN Transmit data input; integrated pull up; LOW: bus becomes dominant, HIGH: bus becomes recessive Pulse Width Modulation control; integrated pull down, active HIGH. To PWM-control highside-switch HS1 Wake-Up input; for detection of external wake-up events within cyclic wake mode, integrated pull down, active HIGH, switches on rising edge
19 24
CLK VCC
25 26 27 28
RxD TxD PWM WK
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Functional Block Diagram
OUTL1 Charge Pu mp Drive OUTL2 Drive Vs Protection + Drive PW M Sw itch Fail Detect OUTH2 Drive
Vcc
OUTH1
OUTH3 CS N
Drive
UVLO
SPI
CLK DI DO Vcc
+ Band Gap
Timer Reset Generator + Window Watchdog
Oscillator
RO
LDO
Vs Vcc
Mode Control
WK
RTL
Fail Management
CA NH CA NL RTH
H Output Stage L Output Stage
Vcc
Driver Temp. Protect Input Stage
TxD
Vcc
Filter
Receiver
RxD
CA N Fail Detect
G ND
Figure 2
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TLE 6266 G Functional Block Diagram
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6
Circuit Description
The TLE 6266 G is a monolithic IC, which incorporates a failure tolerant low speed CANtransceiver for differential mode data transmission, a low dropout voltage regulator for internal and external 5V supply as well as a SPI interface to control and monitor the IC. Further there are three high side switches, two low side switches, a window watchdog circuit and a reset circuit integrated. Figure 2 shows the block diagram of the TLE 6266. 6.1 Operation Modes
The TLE 6266 offers four different operation modes (see Figure 3), that are controlled via the SPI input bits 9,10 (mode bits M0,M1) as shown in Table 1: the normal operation mode, the receive-only mode, the Vbat stand-by mode and the cyclic wake operation mode. The cyclic wake mode itself is subdivided into two modes: the cyclic HS OFF and the cyclic HS ON mode. Cyclic wake and Vbat stand-by mode are both designed for periods that do not require communication on the CAN-Bus but offer a low power mode. The lowest current consumption is achieved in the cyclic wake mode(<70A). Table 1 Operation modes bit settings Mode Bit M1 (SPI Bit 10) Normal operation Cyclic Wake RxD only Vbat stand-by 1 1 0 0 Mode Bit M0 (SPI Bit 9) 1 0 1 0
Normal Operation Mode The normal operation mode is designed to receive and transmit data messages as well as to supply the ECU and control loads via HS- and LS- switches. RTL is switched to VCC, RTH to GND. Table 3 gives an overview about the available functions in this mode. RxD-only Mode In the receive-only mode the receiver stage is activated and the transmitter stage is deactivated. This means that data at the TxD input is not transmitted to the CAN bus but receiving of data is still possible. The CANL line is pulled-up to VCC via the RTL output and CANH is pulled to GND via RTH. This mode is useful in combination to a dedicated network-management software that allows separate diagnosis for all nodes (see Chapter 6.2). Table 3 gives an overview about the available functions in this mode.
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achieve a low power consumption. All other functions are active as in the normal mode (see Table 3). The CANL line is pulled-up to battery supply voltage via the RTL output and CANH pulled to GND via RTH. A wake-up request via a CAN message on the bus is immediately reported to the microcontroller by setting RxD=LOW. The wake pin WK is not active in this mode. A power-on condition (Vbat pin is supplied) or a watchdog reset, automatically switches the TLE 6266 to Vbat stand-by mode. Also if the supply voltage drops below the specified limits (undervoltage reset), the transceiver is automatically switched to Vbat stand-by mode or power down mode, respectively. Cyclic Wake Modes In the cyclic wake operation mode the lowest power consumption is achieved. This mode consists of two states, the Cyclic HS ON and the Cyclic HS OFF mode. In the HS ON state the transmitter, receiver and all switches, except the HS3 switch, are deactivated. The CANL line is pulled-up to battery supply voltage via the RTL output and CANH pulled to GND via RTH. A wake-up via CAN bus message sets the RxD output to LOW. In the HS ON state, a long open window is started. If there is no valid watchdog trigger or a PWM transition into the HS OFF state during this time, a watchdog reset is activated. Only a correct trigger signal on the PWM Pin causes a transition into the cyclic HS OFF state. This is called the "failsafe PWM" feature. In the HS OFF state, almost all functions of the IC are deactivated(also HS3-switch). Only the wake-up input, the oscillator and the power-on reset circuit are activated. The oscillator is used to realize the HS3-cyclic wake function.This automatically switches to HS ON state after a programed time, to enabled HS3 (see Table 2).The CANL line is pulled-up to battery supply voltage via the RTL output and CANH pulled to GND via RTH. Only the wake up via CAN message sets the RxD to low (visible in HS ON state). There are three possibilities to enter the cyclic HS ON mode from the HS OFF mode: * the cyclic wake function * a falling edge at the wake-up pin * a CAN bus wake Table 2 SPI Bit settings for the cyclic wake function Input Bit12 0 1 0 1 Period 48ms 96ms 192ms no cyclic wake-up
8
Vbat stand-by Mode In the Vbat stand-by mode the CAN transmitter and receiver stage are deactivated, to
Input Bit 13 0 0 1 1
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# of Cycles
(1 cycle = 512s typ.)
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Power Down
Start Up Power Up
Normal Mode M1 = 1 M0 = 1
all functions active SPI
SPI SPI
Power ON Reset
SPI
RxD-Only M1 = 0 M0 = 1
SPI all functions active SPI
SPI
Vbat Stand-By M1 = 0 M0 = 0
Vcc = ON RTL = 12V WD = ON POR = ON PWM HS12) 3VSU = ON RxD = H/L
SPI
Cyclic Wake Cyclic HS OFF M1 = 1 M0 = 0
Vcc = OFF/ON POR = ON RTL = 12V RxD = H WD = OFF 3V SV1) = ON HS3 = OFF automatic transition after: - cyclic wake time - WK pin = H PWM3) - CAN bus wake
t>TWDR
Watch dog Reset
SPI
Cyclic HS ON M1 = 1 M0 = 0
Vcc = ON RTL = 12V WD = ON HS3 = ON POR = ON RxD = H/L 3V SV1) = ON SPI SPI
Mode Bits: M0 = SPI Input Bit 9 M1 = SPI Input Bit 10
1) 3V supervisor feature only active if selected via SPI 2) HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM input pin27 if the SPI input bit 11 (PWM enable) is set. In case both controls are active, the HS1 switch is masked by the SPI input bit 1 (see figure 12) 3) this function makes sure that the cyclic HS OFF mode can only be entered via a correct signal at the PWM pin
Figure 3
State Diagram
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Table 3 Feature
Operation mode table Normal mode ON ON ON ON ON ON ON ON ON ON ON OFF ON ON ON OFF OFF ON
switched to Vcc L = bus dominant; H = bus recessive
RxD only mode ON ON ON ON ON OFF ON ON ON ON ON OFF ON ON ON OFF OFF ON
switched to Vcc L = bus dominant; H = bus recessive
Vbat stand-by mode ON ON ON ON ON OFF OFF ON ON ON ON OFF ON ON ON OFF OFF ON
switched to Vs
Cyclic Wake HS ON ON ON ON ON ON OFF OFF OFF OFF OFF OFF ON OFF OFF OFF OFF ON ON
switched to Vs
Cyclic Wake HS OFF OFF/ON ON OFF OFF ON OFF OFF OFF OFF OFF OFF OFF OFF OFF OFF ON OFF ON
switched to Vs active low on CAN message wake-up
LDO Reset Watchdog SPI Oscillator CAN transmit CAN receive OUTHS 11) 2) 3) PWM HS12) OUTHS 21) 3) OUTHS 31) 3) OUTHS 3 cycl. HS ON1) 3) OUTLS 11) 3) OUTLS 2
1) 3)
OUT HS 3 Timebase-Test Wake Pin Failsafe PWM 4) 3V Supervisor 1) RTL output RxD output
active low on active low on CAN message CAN message wake-up wake-up
1) 2)
only active when selected via SPI HS1 is controlled by the SPI input bit 1(activate HS1) and also the PWM input pin27 if the SPI input bit 11 (PWM enable) is set. In case both controls are active, the HS1 switch is masked by the SPI input bit 1 (see figure 12) automatically disabled when a reset resp. watchdog reset occurs this function makes sure that the cyclic HS OFF mode can only be entered via a correct signal at the PWM pin
3) 4)
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6.2
LS CAN Transceiver
The CAN transceiver TLE 6266 works as the interface between the CAN protocol controller and the physical CAN bus-lines. Figure 4 shows the principle configuration of a CAN network.
Controller 1 RxD1 TxD1 RxD2
Controller 2 TxD2
Transceiver1
Transceiver2
BUS Line
Figure 4
CAN Network Example
In normal operation mode a differential signal is transmitted/received. When bus wiring failures are detected, the device automatically switches in a dedicated single-wire mode to maintain communication. While no data is transferred, the power consumption can be minimized by multiple low power operation modes. Further a receive-only mode is implemented that allows a separate CAN node diagnosis. During normal and RxD-only mode, RTL is switched to VCC and RTH to GND. During Vbat stand-by and the cyclic wake mode, RTL is switched to VS and RTH to GND. Receive-only Mode The receive only mode is designed for a special test procedure to check the bus connections. Figure 5 shows a network consisting of 5 nodes. If the connection between node 1 and node 3 shall be tested, the nodes 2,4 and 5 are switched into receive only mode. Node 1 and node 3 are in normal mode. If node 1 sends a message, node 3 is the only node which can acknowledge the message, the other nodes can only listen but cannot send an acknowledge bit. If node 1 receives the acknowledge bit from node 3, the connection is OK. Electromagnetic Emmision (EME) To reduce radiated electromagnetic emission (EME), the dynamic slopes of the CANL and CANH signals are both limited and symmetric. This allows the use of an unshielded twisted or parallel pair of wires for the bus. During single-wire transmission (one of the
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bus lines is affected by a bus line failure) the EME performance of the system is degraded from the differential mode.
5 4
1
3 2
Figure 5 6.3
Testing the Bus Connection in Receive-only Mode
Bus Failure Management
There are 9 different CAN bus wiring failures defined by the ISO 11519-2 standard. These failures are devided into 7 failure groups (see Table 4). When a bus wiring failure is detected the device automatically switches to a dedicated CANH or CANL single-wire mode to maintain the communication if necessary. Therefore it is equipped with one differential receiver and four single ended comparators (two for each bus line). To avoid false triggering by external RF influences, the single wire modes are activated after a certain delay time. As soon as the bus failure disappears the transceiver switches back to differential mode after another time delay. The bus failures are monitored via the diagnosis protocoll of the SPI. Therefore it is possible to distinguish 6 CAN bus failures or failure groups on the SPI output bits 8 to 13 (see Table 4 and 5). The failures are reported until transmission of the next CAN word begins.The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to HIGH resets the SPI diagnosis bit 0. The differential receiver threshold is set to typ. -2.5V. This ensures correct reception in the normal operation mode as well as in the failure cases 1, 2, 3a and 4 with a noise margin as high as possible. When one of the bus failures 3, 5, 6, 6a, and 7 is detected, the defective bus wire is disabled by switching off the affected bus termination and output stage. Simultaneously the multiplexing output of the receiver circuit is switched to the unaffected single ended comparator.
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Table 4 Failure # 1 2 3 4 5 6 7
CAN bus line failure cases (according to ISO 11519-2) Failure Description CANL line interrupted CANH line interrupted CANL shorted to Vbat, CANL > 7.2 V CANH shorted to GND CANL shorted to GND CANH shorted to Vbat; CANH > 7.2 V CANL shorted to CANH
3a (no ISO failure) CANL shorted to Vcc; 3.2 V < CANL < 7.2 V
6a (no ISO failure) CANH shorted to Vcc; 1.8 V < CANH < 7.2 V
In case the transmission data input TxD is permanently dominant, both, the CANH and CANL transmitting stage are disabled after a certain delay time tTxD. This is necessary to prevent the bus from being blocked by a defective protocol unit or short to GND at the TxD input. In order to protect the transceiver output stages from being damaged by shorts on the bus lines, current limiting circuits are integrated. The CANL and CANH output stage respectively are protected by an additional temperature sensor, that disables them as soon as the junction temperature exceeds the maximum value. In the temperature shutdown condition of the CAN output stages receiving messages from the bus lines is still possible. A thermal shutdown of the CAN-transceiver circuit is monitored via the SPI output bit 15. The CANH and CANL pins are also protected against electrical transients which may occur in the severe conditions of automotive environments. Table 5 OBIT 13 12 11 10 9 8 0
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SPI output bits for bus failure diagnosis Bus Failure CAN Failure 2 and 4 CAN Failure 1 and 3a CAN Failure 6 CAN Failure 6a CAN Failure 5 and 7 CAN Failure 3 CAN Bus Failure
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6.4
Low Dropout Voltage Regulator
The TLE6266 is able to drive external 5V loads up to 45 mA. Its output voltage tolerance is less than 2%. In addition the regulator circuit drives the internal loads like the CANtransceiver circuit. In the cyclic wake HS OFF operation mode the voltage regulator is switched on and off by a control mechanism (see Chapter 6.5). The current limitation of the LDO is set to typ. 180mA, to grant that the external capacitor can be charged quickly. In normal operating mode the external current should be less then 45mA. This has to guaranteed by the system architecture. An external reverse current protection is recommended to prevent the output capacitor from being discharged by negative transients or low input voltage. Stability of the output voltage is guaranteed for output capacitors CVCC 100 nF. Nevertheless a lot of applications require a much larger output capacitance to buffer the output voltage in case of low input voltage or negative transients. Furthermore the due function of e.g. the reset and 3V-supervisor circuit are supported by a larger output capacitance because of their reaction times. Therefore a output capacitance CVCC 22 F is recommended. 6.5 LDO activation during Cyclic Wake HS OFF
During the cyclic wake HS OFF mode, the LDO is switched on and off, depending on the output voltage level, which is monitored internaly. Figure 6 shows a detailed flowchart of the Vcc control loop and also a graph of the Vcc voltage and the thresholds in this mode. The voltage regulator is switched on as soon as the voltage at VCC falls below the load-threshold to charge an external capacitor for 1ms. When the nominal voltage level is reached again, the voltage regulator is automatically deactivated to minimize the current consumption. The period of charging/decharging is dependant on the external stabilization capacitor at VCC. 6.6 3V-Supervisor
If the output voltage falls below the 3V-supervisor threshold VST, an internal flip-flop is set LOW. The SPI output bit 7 monitors this. In normal operation this flip-flop has to be activated via the SPI input bit 7. This feature is useful e.g. to monitor that the RAM data of the microcontroller might be damaged or the application is connected to VS the first time. The 3V supervisor uses a comparator to monitor the voltage. Additional, there is a possibility to disable this comparator in order to reduce the current consumption. To do this, set SPI input bit 15 first and in the next step set SPI input bit 7.
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Monitor Vcc in Cyclic wake HS OFF Mode
Vcc Yes 5 4 t tCHARGE Charge Diagram No VCC TH VRESET TH
Vcc
Vcc > load threshold VCC TH ?
Vcc No
Vcc< reset threshold VRESET TH for t > 3s ?
Charge of Vcc for 1ms (Switch on LDO)
Yes RESET after filteringtime
Figure 6 6.7
LDO activation flowchart for the cyclic wake HS OFF mode
SPI (serial peripheral interface)
The 16-bit wide programming word or input word (see Table 6) is read in via the data input DI, and this is synchronized with the clock input CLK supplied by the C. The diagnosis word appears synchroniously at the data output DO (see Table 7). The transmission cycle begins when the chip is selected by the chip select not input CSN (H to L). After the CSN input returns from L to H, the word that has been read in becomes the new control word. The DO output switches to tristate status at this point, thereby releasing the DO bus for other usage. The state of DI is shifted into the input register with every falling edge on CLK. The sate of DO is shifted out of the output register after every rising edge on CLK. For more details of the SPI timing please refer to Figure 11 to 15. CAN Bus Wiring Failure direct Read-out The SPI output bit 0 for CAN bus wiring failure can be read out without SPI transmission directly via the CSN pin (CSN=LOW). A transition of the CSN pin signal from LOW to HIGH resets the SPI diagnosis bit 0. SPI CLK Monitoring during Cyclic Wake Mode The TLE 6266 offers a feature to monitor the SPI clock signal (CLK pin) during the cyclic wake mode. If there are edges on the CLK signal, the IC performs a reset and the RO
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pin is set to LOW for t= tWDR (after tWDR a long open window is started and RO is HIGH again). This feature is activated if the CSN pin is set to HIGH. Table 6 IBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI Input Data Protocol Table 7 OBIT 15 14 13 12 11 10 9 8 7 6 5 4 3 2 1 0 SPI Output Data Protocol
Input Data Disable 3V Reset Comparator not used Cyclic Wake Time Bit2 Cyclic Wake Time Bit1 PWM Enable HS1 Mode 1 Mode 0 not used Supervisor Enable LS-Switch 2 LS-Switch 1 Timebase Test HS-Switch 3 HS-Switch 2 HS-Switch 1 Watchdog Trigger
H=ON L=OFF
Output Data Thermal Shutdown Transceiver Thermal Shutdown Switches CAN Failure 2 and 4 CAN Failure 1 and 3a CAN Failure 6 CAN Failure 6a CAN Failure 5 and 7 CAN Failure 3 3V Supervisor (Vcc < 3V) Status LS2 Status LS1 Temperature Prewarning for all Switches Vs Undervoltage Lockout Window Watchdog Reset Overcurrent HS1 CAN Bus Failure
H=ON L=OFF
6.8
Oscillator
The TLE 6266 has an internal oscillator with +/-15% accuracy. The typ. frequency of the oscillator is 125kHz. After an internal 64-times frequency divider, this gives an typ. cycle time tcyc= 0.512ms. The frequency of the oscillator can be measured within the normal, the Vbat stand-by and the RxD-only mode. This is a timebase test (see Chapter 6.15), activated via SPI input bit 3 and 4. During this test, the HS3-switch will be activated cyclically.
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6.9
Window Watchdog and Reset
When the output voltage VCC exceeds the reset threshold voltage VRT the reset output RO is switched HIGH after a delay time tRD. This is necessary for a defined start of the microcontroller when the application is switched on. As soon as an under-voltage condition of the output voltage (VCC < VRT) appears, the reset output RO is switched LOW again. The LOW signal is guaranteed down to an output voltage VCC 1V. Please refer to Figure 17, reset timing diagram. In the cyclic wake HS OFF mode, the watchdog circuit is automatically disabled.Both, the undervoltage reset and the watchdog reset set all SPI input bits LOW. Long Open Window After the delayed reset (LOW to HIGH transition of RO) the window watchdog circuit is started by opening a long open window. The long open window allows the microcontroller to run his set-up and to trigger the watchdog via the SPI afterwards. Within the long open window period a watchdog trigger is alternating detected as a "rising" or "falling edge" by sampling a HIGH on the SPI input bit 0. The trigger is accepted when the CSN input becomes HIGH after the transmission of the SPI word. After every reset condition (watchdog reset, undervoltage reset) as well as a transition in the cyclic wake mode from HS OFF to HS ON, the watchdog starts the long open window and the default value of the SPI input bit 0 is LOW. Closed/Open Window A correct watchdog trigger immediately results in starting the window watchdog by opening the closed window followed by the open window (see Figure 18). From now on the microcontroller has to service the watchdog trigger by inverting the SPI input bit 0 alternating. The "negative" or "positive" edge has to meet the open window time. A correct watchdog service immediately results in starting the next closed window. Please refer to Figure 19, watchdog timing diagram. Watchdog Trigger Failure If the trigger signal does not meet the open window a watchdog reset is created by setting the reset output RO low for tWDR. Then the watchdog starts again by opening the long open window. In addition, the SPI output bit 2 is set HIGH until the next successful watchdog trigger, to monitor a watchdog reset. SPI output bit 2 is also HIGH until the watchdog is correctly triggered after power-up/start-up. For fail safe reasons the TLE6266 is automatically switched in Vbat stand-by mode if a watchdog trigger failure occurs. 6.10 High Side Switch 1
The high side output OUTH1 is able to switch loads up to 250 mA. Its on-resistance is 1.0 W typ. @ 25C. This switch can be controlled either via the PWM input or the SPI input bit 1. When the input PWM is used, it has to be enabled by setting the SPI input bit
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11 HIGH. In case of both control inputs being active the PWM signal is masked by the SPI signal (see Figure 16, High Side Switch 1 Timing Diagram). The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit 4 flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation of the TLE 6266 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. Further OUTH1 is protected against short circuit and overload. The SPI output bit 1 indicates an overload of OUTH1. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI output bit 3. Moreover the switch is disabled when a reset occurs. After the second correct triggered watchdog, the switch is released for usage. 6.11 High Side Switch 2
The high side output OUTH2 is able to switch loads up to 250 mA. Its on-resistance is 1.0 W typ. @ 25C. This switch is controlled via the SPI input bit 2. The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit 4 flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation of the TLE 6266 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI output bit 3. Moreover the switch is disabled when a reset occurs. After the second correct triggered watchdog, the switch is released for usage. 6.12 High Side Switch 3
The high side output OUTH3 is able to switch loads up to 250 mA. Its ON-resistance is 1.0 W typ. @ 25C. This switch is controlled via the SPI input bits 3 and 4. To supply external wake-up circuits in low power mode (cyclic wake mode), the output OUTH3 is periodically activated by entering the cyclic wake HS ON mode. The autotiming period is programable via SPI (see Table 2).This has to be done, to minimize the current consumption depending on the cyclic wake time (see Figure 21). In the cyclic wake mode, the PWM signal is used to switches HS3 from the cyclic HS ON to the cyclic HS OFF state, if correctly triggered within the long open window (see Figure 17). This is called the "fail-safe PWM" feature The SPI output bit 14 monitors a thermal shutdown of the switches, whereas output bit 4 flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation of the TLE 6266 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. As soon as the under-voltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI output bit 3.
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Moreover the switch is disabled when a reset occurs. After the second correct triggered watchdog, the switch is released for usage. 6.13 Low Side Switches 1 & 2
The two low side outputs OUTL1 and OUTL2 are able to switch loads up to 100 mA. Their on-resistance is 1.5 W typ. @ 25C. This switches are controlled via the SPI input bits 5 and 6. In case of high inrush currents a built in zener circuit (typ. 37 V) activates the switches to protect them. The SPI diagnosis bit 14 monitors a thermal shutdown of the switches, whereas bit 4 flags a thermal prewarning. So the microcontroller is able to reduce the power dissipation of the TLE 6266 by switching off functions of minor priority before the temperature threshold of the thermal shutdown is reached. The SPI output bits 5/6 are giving a feedback about current status (ON/OFF) of OUTL1/OUTL2. As soon as the undervoltage condition of the supply voltage is met (VS < VUVOFF), the switches are automatically disabled by the under-voltage lockout circuit. This is flagged by the SPI diagnosis bit 3. In addition the outputs OUTL1 and OUTL2 are disabled when a reset occurs. After the second correct triggered watchdog, the switches are released for usage. 6.14 Wake Up Pin
This pin is used to wake up the TLE 6266 with an external signal from the C. The feature is active during cyclic HS OFF mode to switch the transceiver into the cyclic HS ON mode before starting up the C. A correct wake up signal is a rising edge at the WK pin during cyclic HS OFF mode. The WK pin has an implemented pull down resistance. 6.15 Timebase Test
This test is useful to measure the internal cycle time of the TLE 6266. The C may use this information to activate special functions or routines in the cyclic wake mode, which are depending on timing.(e.g. to switch on/off a LED after a certain number of cyclic HS ON conditions). During the long open window the timebase test is not available. To measure the internal cyclic timing, the SPI input bit 3 and 4 have to be set HIGH. Then the HS3 switch is automatically enabled for 3 times during the closed window of the watchdog (see Figure 7). A correct SPI input word (with IBit 3 and 4 set HIGH) has to be read in first, to activate the timebase test. Due to he fact, that the input command gets activated after the CSN LOW to HIGH transition, it takes t=tSYNC to activate the timebase test. If this SPI input command is given within the open window, tSYNC=max 500ns. If the command is given during closed window (this is not a watchdog trigger command) the synchronisation tSYNC can last up to 500s.
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HS3
ON
closed window (12 cycles)
2cycl. 2cycl. 2cycl.
OFF
2cycl.
2cycl.
2cycl.
t
CSN
t SYNC
SPI Input word with timebase test command
t
Figure 7 6.16
Timebase Test Diagram
Flash program mode
To disable the watchdog feature a flash program mode is available. This mode is selected by applying a voltage of 6.8V < VPWM < 7.2V at pin PWM. This is useful e.g. if the flash-memory of the micro has to be programmed and therefore a regular watchdog triggering is not possible. If the SPI is required in the flash program mode to change e.g. the mode of the TLE6266, the first input telegram has to be "00000000".
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7
Explanation of the Mode Transitions
To better understand the description, the reader has to be familiar with the Chapter 6. All descriptions are starting from the normal mode, as the main operation mode. This means, the component was powered up before and after the power up procedure automaticaly in the Vbat stand-by mode. Now, the watchdog circuit has to be operated correctly to switch the component in the other modes ( details see Chapter 6). So the starting point is the TLE 6266 in normal mode with a correct triggered watchdog like shown in Figure 8,9,10. Normal Mode and Cyclic HS ON In normal mode, the watchdog has to be triggered within the open window with a dedicated SPI input command (Watchdog Trigger IBit 0, alternatively HIGH, LOW,...). The CAN bus communication is active and a message can be transfered/received. After the correct SPI input command to change into the Cyclic HS mode, the HS3 switch gets activated. In parallel a long open window is started, wich has to be triggered. This mode can be operated as long as the watchdog is triggered correctly. In this mode, no communication is possible but an external circuit can be supplied by HS3. CANL is pulled up to Vs by the RTL termination, CANH is pulled to GND via RTH. Cyclic HS OFF mode To switch from HS ON to HS OFF, the PWM input has to be triggered with a falling egde. This is called the PWM failsafe trigger to avoid unwanted transitions into the HS OFF mode. In the HS OFF mode the HS3 switch is deactivated and the lowest power consumption is achieved. The LDO monitors Vcc and switches on/off due to a special control mechanism explained in Chapter 6.5. Three possibilities can switch the TLE 6266 back to the cyclic wake HS ON mode: 7.1 CAN Bus Wake-Up
CANL is pulled to Vs. A signal transition at CANL below a certain wake-up threshold causes a wake up and automatic transition into the cyclic HS ON mode (see Figure 8). HS3 is activated again and also the long open window of the watchdog mechanism. The watchdog has to be triggered correctly from that time on. If the signal at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again. This wake up via the CAN bus message is flagged to the C by setting the RxD output pin from HIGH to LOW. The reason for this behavior is to indicate the C a wake up request. Now, the C is able to activate the whole module to serve the requested action by the bus system.
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Mode State Normal Mode CSN, SPI word*
SPI normal mode SPI cyclic HS ON SPI cyclic HS ON SPI normal mode
Normal Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
Normal Mode
Vbat Stdby
t
Watchdog trigger bit =SPI bit0**
t Window watchdog***
closed window open window closed window open window long open window long open window closed window open window closed window missing trigger = timeout = Watchdog Reset open window long open window
Watchdog reset pulse time tWDR
t
HS3
t PWM
PWM trigger
PWM trigger Vs Vcc Bus Wake trigger CAN Bus message
t
CANL CANH
Input filtering time tIFT
t
* for the exact timing relations between CSN and SPI-DI and -DO word please look at datasheet fig. 11,12,13,14,15
** bit0 is transfered with the SPI input word BUT the watchdog trigger is set, after readout of the SPI input bit = CSN LOW to HIGH (see arrows at CSN signal)
*** for a correct watchdog triggering: closed window must always exceed 12 cycles open window is max. 20 cycles long open window is max. 128 cycles otherwise a watchdog reset will be generated
Figure 8 7.2
Cyclic Wake with CAN Message Wake-up
Wake-Up via Wake Pin
CANL is pulled to Vs. A signal transition at the wake pin WK from LOW to HIGH (rising edge) causes a wake up and automatic transition into the cyclic HS ON mode (see Figure 9). HS3 is activated again and also the long open window of the watchdog mechanism. The watchdog has to be triggered correctly from that time on. If the signal at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again. This wake up via the wake pin is comming from an external circuitry (switch, etc.) and is not flagged by the RxD.
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Mode State Normal Mode CSN, SPI word*
SPI normal mode SPI cyclic HS ON SPI cyclic HS ON SPI normal mode
Normal Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
Normal Mode
Vbat Stdby
t
Watchdog trigger bit =SPI bit0**
Window watchdog***
closed window open window closed window open window long open window long open window closed window open window closed window
missing trigger = timeout = Watchdog Reset open window
t
long open window
Watchdog reset pulse time tWDR
t
HS3
t PWM
PWM trigger
PWM trigger
t Wake
wake trigger
Wake event
Input filtering time tIFT
t
* for the exact timing relations between CSN and SPI-DI and -DO word please look at datasheet fig. 11,12,13,14,15
** bit0 is transfered with the SPI input word BUT the watchdog trigger is set, after readout of the SPI input bit = CSN LOW to HIGH (see arrows at CSN signal)
*** for a correct watchdog triggering: closed window must always exceed 12 cycles open window is max. 20 cycles long open window is max. 128 cycles otherwise a watchdog reset will be generated
Figure 9 7.3
Cyclic Wake with Wake Pin
Wake-Up Cyclic Wake Autotiming Function
CANL is pulled to Vs. After the transition from HS ON to HS OFF, an autotiming function is started. This is a timer controled by the internal oscillator, which can be programed by SPI IBit 12,13. If the timer exceeds the programed time this causes a wake up and automatic transition into the cyclic HS ON mode (see Figure 10). HS3 is activated again and also the long open window of the watchdog mechanism. The watchdog has to be triggered correctly from that time on. If the signal at the PWM pin makes a HIGH to LOW transition, the device switches to HS OFF again. This wake up via the autotiming function is not flagged to the C by setting the RxD pin.
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Mode State Normal Mode CSN, SPI word*
SPI normal mode SPI cyclic HS ON SPI cyclic HS ON SPI normal mode
Normal Mode
Cyclic HS ON
Cyclic HS OFF
Cyclic HS ON
Cyclic HS ON
Normal Mode
Vbat Stdby
t
Watchdog trigger bit =SPI bit0**
Window watchdog***
closed window open window closed window open window long open window long open window closed window open window closed window
missing trigger = timeout = Watchdog Reset open window
t
long open window
HS3
Cyclic wake time 48ms selected
48ms
Watchdog reset pulse time tWDR
t
t PWM
PWM trigger
PWM trigger
t
* for the exact timing relations between CSN and SPI-DI and -DO word please look at datasheet fig. 11,12,13,14,15 ** bit0 is transfered with the SPI input word BUT the watchdog trigger is set, after readout of the SPI input bit = CSN LOW to HIGH (see arrows at CSN signal) *** for a correct watchdog triggering: closed window must always exceed 12 cycles open window is max. 20 cycles long open window is max. 128 cycles otherwise a watchdog reset will be generated
Figure 10
Cyclic Wake with Cyclic Wake Autotiming Function
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8 8.1
Electrical Characteristics Absolute Maximum Ratings Symbol Limit Values min. max. Unit Remarks
Parameter
Voltages Supply voltage Supply voltage Regulator output voltage CAN input voltage (CANH, CANL) CAN input voltage (CANH, CANL) Transient voltage at CANH and CANL
VS VS VCC VCANH/L VCANH/L VBUS
-0.3 -0.3 -0.3 -10 -40 - 150 -0.3
28 40 5.5 28 40 100
V V V V V V V V V V V
human body model; C = 100pF, R = 1.5kW human body model; C = 100pF, R = 1.5kW VS >0 V tp< 0.5s; tp/T < 0.1 see ISO 7637 tp< 0.5s; tp/T < 0.1
Logic input voltages ( DI, CLK, VI CSN, WK, PWM, TxD) Logic output voltage (DO, RO, RxD) Termination input voltage (RTH, RTL) Electrostatic discharge voltage at pin CANH, CANL Electrostatic discharge voltage to any other pin Currents Output current; Vcc Output current; OUTH1 Output current; OUTH2 Output current; OUTH3 Output current; OUTL1 Output current; OUTL2
VCC
+0.3
VDO/RO/RD -0.3 VTL /TH VESD VESD
-0.3 -4000 -2000
VCC
+0.3
VS
+0.3 4000 2000
ICC IOUTH1 IOUTH2 IOUTH3 IOUTL1 IOUTL2
* * -0.7 -0.7 -0.2 -0.2
0,2 0.3 0.3 0.3 0.4 0.4
A A A A A A
* internally limited * internally limited tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1 tp< 0.5s; tp/T < 0.1
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8.1
Absolute Maximum Ratings (cont'd) Symbol Limit Values min. max. Unit Remarks
Parameter
Temperatures Junction temperature Storage temperature
Tj Tstg
-40 -50
150 150
C C
Note: Maximum ratings are absolute ratings; exceeding any one of these values may cause irreversible damage to the integrated circuit.
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8.2
Operating Range Symbol Limit Values min. max. V V/ms
Outputs in tristate Outputs in tristate After VS rising above VUV ON
Parameter Supply voltage Supply voltage slew rate Supply voltage increasing Supply voltage decreasing Logic input voltage (DI, CLK, CSN, PWM, TxD ) Output current Output capacitor SPI clock frequency Junction temperature Thermal Resistances Junction pin Junction ambient
Unit
Remarks
VS
dVS /dt
VUV OFF 27
-0.5 -0.3 -0.3 -0.3 5
VS VS VI ICC CCC fCLK Tj
VUV ON V VUV OFF V VCC V
45 mA mF 1 150 MHz C
22 - -40
Rthj-pin Rthj-a
- -
25 65
K/W K/W
measured to pin 7
Thermal Prewarning and Shutdown (junction temperatures) Thermal prewarning ON temperature Thermal shutdown temp. Ratio of SD to PW temp.
TjPW TjSD
120 150 135
170 200 - 160
C C - C
bit 0 of SPI diagnosis word; hysteresis 30K (typ.) hysteresis 30K (typ.)
TjSD / TjPW 1.05
Thermal shutdown temp. CAN TjSD
hysteresis 10K (typ.)
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8.3
Electrical Characteristics
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Quiescent current Pin VS Current consumption Quiescent current
ISSB1 = IS - ICC
Static quiescent current Voltage Regulator; Pin VCC Output voltage Output voltage Line regulation Load regulation
IS ISSB1 ISTAT
- - -
8 75 -
10 100 70
mA mA mA
normal mode cycl. wake 48ms; VS=12V; Tj=25C
VCC VCC ,VCC ,VCC
4.9 4.8 -20 -25
5.0 5.0
5.1 5.5 20 25
V V mV mV dB
0.1mA < ICC< 30mA 0A < ICC < 100A 9 V < VS < 15 V; ICC = 10mA 0.1mA < ICC< 30mA; VS = 9V VS < 1 Vss; CQ 22F; 100Hz< f <100kHz 1) ICC = 30 mA; see note 1)
Power supply ripple rejection PSRR Output current limit Dropvoltage
40 155 0.15 0.45
VDR = VS - VCC
Wake-up Input WK Input current H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Input filtering time
ICCmax VDR
mA V
IIL VIH
-3 -
-2 -
-1
mA
0.7 V
VCC
VIL VIHY tIFT
0.2 -
- 500 3
V mV s
VCC
50 -
200 -
1) measured when output voltage VCC dropped 100 mV from the nom. value obtained at 13.5 V inp. voltage VS
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Oscillator Oscillator frequency fosc Cycle time (guaranteed by design) Reset Generator; Pin RO Reset threshold voltage Reset low output voltage
fOSC tCYC
125 512
kHz s
+/-15% accuracy 64 times frequency divider
VRT VRO
4.0
4.3 0.2
4.65 0.4
V V
IRO = 1mA (VCC VRT) or VCC 1V (IRO = 200 A)
Reset high output voltage Reset pull up current Reset reaction time Reset reaction time Reset delay time (16 cyl.)
VRO IRO tRR tRR tRD
4.0 20 1 - 6.1 150 3 - 8.1
VCC+ V
0.1 500 10 50 10.2 mA s s ms
VRO = 0V VCC < VRT to RO = L; normal, RxD, stand-by mode VCC < VRT to RO = L; cyclic wake mode
3 V Supervisor; (bit 7 of SPI output word) Supervisor threshold voltage VST Supervisor reaction time 2.3 2 2.7 8 3.1 20 V s
VCC < VST to diagnosis bit 7 = L
tSR
Watchdog Generator
tWD Closed window time (12 cyl.) tCW
Watchdog trigger time
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12.3 7.6
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Open window time (20 cyl.) Watchdog reset-pulse time (4 cyl.)
Symbol
Limit Values min. typ. 10.2 2.0 65 max. 12.7 2.6 7.7 1.5
Unit Test Condition ms ms ms
tOW tWDR
Long open window (128 cyl.) tLOW
Under-Voltage Lockout (bit 3 of SPI output word) UV-Switch-ON voltage UV-Switch-OFF voltage UV-ON/OFF-Hysteresis
VUV ON VUV OFF VUV HY
- 4.50 -
5.35 4.85 0.5
6.00 5.20 -
V V V
VS increasing VS decreasing VUV ON - VUV OFF
PWM Input to control OUTH1; Pin PWM (high active) H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull down current Input capacitance
VIH VIL VIHY II CI
-
-
0.7 V
VCC
0.2 - Vcc 50 5 - 200 25 10
- 500 180 15
V mV mA pF
VI = 0.2 * VCC 0 V < VCC < 5.25 V
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Switches High Side Output OUTH1; (controlled by PWM or bit 1 of SPI input word) Static Drain-Source ON-Resistance; IOUTH1 = -0.25 A Active zener voltage
RDSON H1 -
1.0 1.5
2.0 4.0 -0.5 1 - 100 100 -0.3 50 -0.5
W W V V A ms ms A ms A
5.2 V VS 9 V IOUTH1 = - 0.25 A IOUTH1 = 0.25 A VOUTH1 = 0 V PWM to OUTH1; RL = 100 W PWM to OUTH1; RL = 100 W
VOUTH1 Clamp diode forward voltage VOUTH1 Leakage current IOLH1 Switch ON delay time tdONH1
Switch OFF delay time Overcurrent shutdown threshold Shutdown delay time Current limit
-5.0 -100
-3.0 0.8 -5 10 20
tdOFFH1 ISDH1 tdSDH1 IOCLH1
-1.0 10 -2.0
-0.6 25 -1.0
High Side Output OUTH2; (controlled by bit 2 of SPI input word) Static Drain-Source ON-Resistance; IOUTH2 = -0.25 A Active zener voltage
RDSON H2 -
1.0 1.5
2.0 4.0 -0.5 1 - 100 100
W W V V A s s
5.2 V VS 9 V IOUTH2 = - 0.25 A IOUTH2 = 0.25 A VOUTH2 = 0 V CSN high to OUTH2; RL = 100 W CSN high to OUTH2; RL = 100 W
VOUTH2 Clamp diode forward voltage VOUTH2 Leakage current IOLH1 Switch ON delay time tdONH1
Switch OFF delay time
-5.0 -100
-3.0 0.8 -5 10 20
tdOFFH1
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
High Side Output OUTH3; (controlled by bit 3 and bit 4 of SPI input word) Static Drain-Source ON-Resistance; IOUTH3 = -0.25 A Active zener voltage
RDSON H3 -
1.0 1.5
2.0 4.0 -0.5 1 - 100 100
W W V V A s s
5.2 V VS 9 V IOUTH3 = - 0.25 A IOUTH3 = 0.25 A VOUTH3 = 0 V CSN high to OUTH3; RL = 100 W CSN high to OUTH3; RL = 100 W
VOUTH3 Clamp diode forward voltage VOUTH3 Leakage current IOLH3 Switch ON delay time tdONH3
Switch OFF delay time
-5.0 -100
-3.0 0.8 -5 10 20
tdOFFH3
Low Side Output OUTL1 ( bit 5 of SPI input word) Static Drain-Source ON-Resistance; IOUTL1 = 0.1 A Active zener clamp voltage Leakage current Switch ON delay time Switch OFF delay time
RDSON L1
-
1.5 2.0
3.0 5.0 42 5
W W V A s s
5.2 V VS 9 V IOUTL1 = + 0.1 A VOUTL1 =15 V; Tj < 85C CSN high to OUTL1; RL = 100 W CSN high to OUTL1; RL = 100 W
VOUTL1 IOLL1 tdONL1 tdOFFL1
32
37
5 5
50 50
Low Side Output OUTL2 ( bit 6 of SPI input word) Static Drain-Source ON-Resistance; IOUTL2 = 0.1 A
Version 1.06
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-
1.5 2.0
3.0 5.0
W W
5.2 V VS 9 V
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Active zener clamp voltage Leakage current Switch ON delay time Switch OFF delay time
Symbol
Limit Values min. typ. 37 max. 42 5 5 5 50 50 32
Unit Test Condition V A s s
IOUTL2 = + 0.1 A VOUTL2 =15 V; Tj < 85C CSN high to OUTL2; RL = 100 W CSN high to OUTL2; RL = 100 W
VOUTL2 IOLL2 tdONL2 tdOFFL2
Timebase Test TBT(bit 4 of SPI input word) HS3 ON timing HS3 OFF timing # of HS activations for TBT
tTBON tTBOFF nTBT
2
2 2
cycl. cycl.
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
CAN-Transceiver Receiver Output RD HIGH level output voltage LOW level output voltage Transmission Input TD HIGH level input voltage threshold LOW level input voltage threshold HIGH level input current LOW level input current Bus Lines CANL, CANH Differential receiver recessive-to-dominant threshold voltage Differential receiver dominant-to-recessive threshold voltage CANH recessive output voltage CANL recessive output voltage CANH dominant output voltage
VdRxD(rd) - 2.8 - 2.5 - 2.2 V
VCC = 5.0 V
VOH VOL
VCC
0
- -
- 0.9
VCC
0.9
V V
I0 = - 250A
I0 = 1.25mA
VIH VIL IIH IIL
0.7 -
VCC
-0.3
VCC VCC
V
+ 0.3
- -50 -200
0.3 V -10 -40 A A
Vi = 4 V Vi = 1 V
-200 -800
VdRxD(dr) - 3.2 - 2.9 - 2.6 V
VCC = 5.0 V
VCANH,r VCANL,r
0.10
0.15
0.30 -
V V V
TxD = VCC; RRTH < 4 kW TxD = VCC; RRTL < 4 kW TxD = 0 V; ICANH = - 40 mA
VCC - - 0.2
VCANH,d VCC VCC VCC - 1.4 - 1.0
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter CANL dominant output voltage CANH output current
Symbol
VCANL,d ICANH
Limit Values min. - typ. 1.0 max. 1.4 - 50 5 110 5 8.0
Unit Test Condition V mA mA mA mA V
TxD = 0 V; ICANL = 40 mA VCANH = 0 V; TxD = 0 V cycl. wake mode; VCANH = 12 V VCANL = 5 V; TxD = 0 V cycl. wake mode; VCANL = 0 V; VS = 12 V
- 110 - 80 -5 0 80 0 7.3
CANL output current
ICANL
50 -5
Voltage detection threshold Vdet(th) for short-circuit to battery voltage on CANH and CANL Voltage detection threshold for short-circuit to battery voltage on CANH CANH wake-up voltage threshold CANL wake-up voltage threshold Wake-up voltage threshold hysteresis
Vdet(th)
6.5
VBAT VBAT - 2.5 - 2
VBAT -1
V
stand-by/ cycl. wake mode
VCANH,w 1.2
u
1.9 3.1 - 2.1 2.9 0 0
2.7 3.9 - 2.6 3.4 5 5
V V V V V mA mA
DVwu = VCANL,wu - VCANH,wu failure cases 3, 5 and 7 failure case 6 and 6a
VCANL,w 2.2
u
DVwu
0.2 1.6 2.4 -5 -5
CANH single-ended receiver VCANH threshold CANL single-ended receiver threshold CANL leakage current CANH leakage current
VCANL ICANL,lk ICANH,lk
VCC = 0 V; VS = 0 V; VCANL = 12 V; Tj < 85 C VCC = 0 V; VS = 0 V; VCANH = 5 V; Tj < 85 C
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
Termination Outputs RTL, RTH RTL to VCC switch-on resistance RTL output voltage RTL to BAT switch series resistance RTH to ground switch-on resistance RTH output voltage RTH pull-down current RTL pull-up current RTH leakage current
RRTL VoRTL RoRTL RRTH VoRTH IRTH,pd IRTL,pu IRTH,lk
-
40
95
W V kW W V mA mA mA
Io = - 10 mA |Io| < 1 mA; VBAT stand-by or cycl. wake mode Io = 10 mA Io = 1 mA; low power mode failure cases 6 and 6a failure cases 3, 3a, 5 and 7 VCC = 0 V; VS = 0 V; VRTH = 5 V; Tj < 85 C VCC = 0 V; VS = 0 V; VRTL = 12 V; Tj < 85 C
VCC VCC - - 1.0 - 0.7
5 - - 40
15 40 0.7 75
30 95 1.0 120 - 40 5
- 120 - 75 -5 0
RTL leakage current
IRTL,lk
-5
0
5
mA
CAN-Transceiver Dynamic Characteristics CANH and CANL bus output trd transition time recessive-todominant CANH and CANL bus output tdr transition time dominant-torecessive 0.6 1.2 2.1 s
10% to 90%; C1 = 10 nF; C2 = 0; R1 = 100 W 10% to 90%; C1 = 1 nF; C2 = 0; R1 = 100 W
0.3
0.6
1.3
s
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Minimum dominant time for wake-up on CANL or CANH Minimum wake-up time on pin WK (wake-up) Failure cases 3 and 6 detection time Failure case 6a detection time Failure cases 5, 6, 6a and 7 recovery time Failure cases 3 recovery time Failure cases 5 and 7 detection time Failure cases 5 detection time Failure cases 6, 6a and 7 detection time Failure cases 5, 6, 6a and 7 recovery time
Symbol
Limit Values min. typ. 22 25 45 4 45 500 2.0 1.0 4.0 2 1.5 max. 38 50 80 8 80 750 4.0 2.4 8.0 - 2.1 8 15 10 2 10 250 1.0 0.4 0.8 - -
Unit Test Condition s s s ms s s ms ms ms s s
stand-by mode; VS = 12 V Low power mode; VS = 12 V normal operating mode normal operating mode normal operating mode normal operating mode normal operating mode stand-by mode; VS = 12 V stand-by mode; VS = 12 V stand-by mode; VS = 12 V C1 = 100 pF; C2 = 0; R1 = 100 W; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 W; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 =100 W; bus failure cases 3, 5, 6, 6a and 7
twu(min)
tWK(min)
tfail
Propagation delay tPD(L) TxD-to-RxD LOW (recessive to dominant)
-
1.7
2.4
s
- -
1.8 2.0
2.5 2.6
s s
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8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter Propagation delay TxD-to-RxD HIGH (dominanat to recessive)
Symbol
Limit Values min. typ. 1.2 max. 2.0 -
Unit Test Condition s
C1 = 100 pF; C2 = 0; R1 =100 W; no failures and bus failure cases 1, 2, 3a and 4 C1 = C2 = 3.3 nF; R1 = 100 W; no bus failure and failure cases 1, 2, 3a and 4 C1 100 pF; C2 = 0; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7 C1 = C2 = 3.3 nF; R1 = 100 W; bus failure cases 3, 5, 6, 6a and 7
tPD(H)
-
2.5
3.5
s
- - Minimum hold time to go sleep command
1.0 1.5 25 4
2.1 2.6 50 -
s s s -
th(min)
15 -
Edge-count difference ne (falling edge) between CANH and CANL for failure cases 1, 2, 3a and 4 detection Edge-count difference (rising edge) between CANH and CANL for failure cases 1, 2, 3a and 4 recovery TxD permanent dominant disable time
normal operating mode
-
2
-
-
tTxD
1.0
2.0
3.5
ms
normal mode
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Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter
Symbol
Limit Values min. typ. max.
Unit Test Condition
SPI-Interface Logic Inputs DI and CSN H-input voltage threshold L-input voltage threshold Hysteresis of input voltage Pull up current at pin CSN Pull down current at pin DI Input capacitance at pin CSN, DI Logic Output DO H-output voltage level L-output voltage level Tri-state leakage current Tri-state input capacitance
VIH VIL VIHY IICSN IICLK/DI CI
-
-
0.7 V
VCC
0.2 -
- 500 -5 100 15
V mV mA mA pF
VCSN = 0.7 VCC VDI = 0.2 VCC 0 V < VCC < 5.25 V
VCC
50
200 -25 25 10
-100 5 -
VDOH VDOL IDOLK CDO
VCC
- -10 -
VCC
0.2 - 10
- 0.4 10 15
V V mA pF
IDOH = 1 mA IDOL = - 1.6 mA VCSN = VCC 0 V < VDO < VCC VCSN = VCC 0 V < VCC < 5.25 V
- 1.0 - 0.7
Data Input Timing Clock period Clock high time Clock low time Clock low before CSN low CSN setup time
Version 1.06
tpCLK tCLKH tCLKL tbef tlead
1000 500 500 500 500
39
- - - - -
- - - - -
ns ns ns ns ns
2002-11-26
Target Datasheet TLE 6266
8.3
Electrical Characteristics (cont'd)
9 V < VS < 16 V; ICC = -100 mA; normal mode; all outputs open; - 40 C < Tj < 150 C; CANtransceiver circuitry: - 40 C < Tj < 125 C; all voltages with respect to ground; positive current defined flowing into pin; unless otherwise specified.
Parameter CLK setup time Clock low after CSN high DI setup time DI hold time Input signal rise time at pin DI, CLK and CSN Input signal fall time at pin DI, CLK and CSN Data Output Timing DO rise time DO fall time DO enable time DO disable time DO valid time
Symbol
Limit Values min. typ. - - - - - - max. - - - - 200 200 500 500 250 250 - -
Unit Test Condition ns ns ns ns ns ns
tlag tbeh tDISU tDIHO trIN tfIN
trDO tfDO tENDO tDISDO tVADO
- - - - -
50 50 - - 100
100 100 250 250 250
ns ns ns ns ns
CL = 100 pF CL = 100 pF low impedance high impedance VDO < 0.2 VCC; VDO > 0.7VCC; CL = 100 pF
Version 1.06
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Target Datasheet TLE 6266
9
Timing Diagrams
CSN High to Low & rising edge of CLK: DO is enabled. Status information is transfered to Output Shift Register
CSN time CSN Low to High: Data from Shift-Register is transfered to Output Power Switches
CLK
0
1
2
3
4
5
6
7
8
9
10 11 12
13 14 15
0
1
actual Data DI 0 1 2 3 4 5 _ 6 7 8 9 10 11 12 13 14 15
new Data 0 + 1 +
DI: Data will be accepted on the falling edge of CLK-Signal previous Status DO _ 0 _ 1 _ 2 _ 3 _ 4 _ 5 _ 6 _ 7 _ 8 _ 9 ___ 10 11 12 ___ 13 14 15 actual Status 0 1
DO: State will change on the rising edge of CLK-Signal
eg. HS1
old Data
actual Data
Figure 11
Data Transfer Timing
Version 1.06
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Target Datasheet TLE 6266
Figure 12
SPI-Input Timing
Figure 13
Turn OFF/ON Time
Version 1.06
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Target Datasheet TLE 6266
Figure 14
DO Valid Data Delay Time and Valid Time
Figure 15
DO Enable and Disable Time
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Target Datasheet TLE 6266
SPI input bit 1
H
L
PWM (SPI input bit 11 = H)
t
H
L
HSSwitch1
t
ON
OFF
t
Figure 16
High Side Switch1 Timing Diagram
Vbat stand-by mode ON Cyclic HS ON Vbat stand-by mode Cyclic HS ON
Cyclic Wake Mode Cyclic HS OFF
Cyclic Wake
OFF Correct Trigger H
PWM
No Trigger
t
L
HSSwitch3
t
ON
OFF
RO
H
Cyclic Wake Time
Long Open Window tLOW
t
tWDR L
Figure 17
Version 1.06
Cyclic Wake Timing Diagram
44 2002-11-26
Target Datasheet TLE 6266
tWD tCW tOW
closed window
open window
t / ms
Figure 18
Watchdog Timeout Definitions
tCW WD Trigger tCW tOW
tOW tCW+tOW tCW+tOW tCW tOW
tCW
tOW tCW
tCW tCW tOW
Reset Out
tWDR
t
Watchdog timer reset
t
normal operation
timeout (to long)
normal operation
timeout (to short)
normal operation
Figure 19
Watchdog Timing Diagram
Version 1.06
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Target Datasheet TLE 6266
Vcc
VRT VST
t < tRR
WD Trigger
tRD
tCW+tOW
tCW
tOW
tCW
tOW
tRD
tCW+tOW
t
Reset Out
tWDR
tRR
t
SPI output bit 2
Watchdog timer reset
t normal operation tSR undervoltage start up
start up
HIGH
LOW activation by microcontroller
t
Figure 20
Reset Timing Diagram
Current Consumption (typ.)
76 75 74 Current (A) 73 Current (A) typ. 72 71 70 69 10 48 100 1000 10000 Cyclic Wake Time (ms) "Static" Current
Figure 21
Version 1.06
Current Consumption during Cyclic Wake Mode
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Target Datasheet TLE 6266
5V C1 C2 C1 R1 R1 RTH CANH CANL RTL OUTL1 OUTL2 OUTH1 OUTH2 OUTH3 13.5 V 100 nF +VS GND
RxD TxD 20 pF CSN DO CLK DI PWM RO WK VCC 22 F
Figure 22
Timing Test Circuit
Version 1.06
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Target Datasheet TLE 6266
10
Application
Vbat
CAN bus
+VS
33 V 22 F 68 nF
CSN CLK DI
CANH CANL
DO TxD RxD
RTH PWM RTL RO OUTL2 OUTL1 OUTH3 OUTH2 OUTH1 WK GND Vcc
22 F
C e.g. Infineon C164
GND
TLE 6266 G
Figure 23
Application Circuit
Version 1.06
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Target Datasheet TLE 6266
11
Package Outlines
P-DSO-28-6 (Plastic Dual Small Outline Package)
Figure 24
The P-DSO-28-6 package
Sorts of Packing Package outlines for tubes, trays etc. are contained in our Data Book "Package Information". Dimensions in mm Version 1.06 49 2002-11-26
GPS05123
Target Datasheet TLE 6266
Edition 1999-10-12 Published by Infineon Technologies AG St.-Martin-Strasse 53 D-81541 Munchen (c) Infineon Technologies AG1999 All Rights Reserved.
Attention please! The information herein is given to describe certain components and shall not be considered as warranted characteristics. Terms of delivery and rights to technical change reserved. We hereby disclaim any and all warranties, including but not limited to warranties of non-infringement, regarding circuits, descriptions and charts stated herein. Infineon Technologies is an approved CECC manufacturer. Information For further information on technology, delivery terms and conditions and prices please contact your nearest Infineon Technologies Office in Germany or our Infineon Technologies Representatives worldwide (see address list). Warnings Due to technical requirements components may contain dangerous substances. For information on the types in question please contact your nearest Infineon Technologies Office. Infineon Technologies Components may only be used in life-support devices or systems with the express written approval of Infineon Technologies, if a failure of such components can reasonably be expected to cause the failure of that life-support device or system, or to affect the safety or effectiveness of that device or system. Life support devices or systems are intended to be implanted in the human body, or to support and/or maintain and sustain and/or protect human life. If they fail, it is reasonable to assume that the health of the user or other persons may be endangered.
Version 1.06
50
2002-11-26
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http://www.infineon.com
Published by Infineon Technologies AG

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